The present invention relates generally to design automation, and relates more particularly to static timing analysis of integrated circuit (IC) chips.
For static timing analysis to be efficient, the various constituent gates of a very large scale integration (VLSI) design must have their timing properties pre-characterized. A typical gate library consists of a thousand or more gates, each representing a different logic function, drive strength, transistor topology, or the like. For each of these gates, the timing properties are typically characterized by running repeated simulations for different input waveforms (“characterization waveforms”) and different capacitive loads. The resulting gate delays and output slews are then tabulated (or fit) as functions of input slew and output load capacitance.
Once the library is characterized, static timing analysis tools use the pre-computed and tabulated timing properties to time each gate in the design. In particular, the input waveform appearing at the switching input of a gate under analysis (“timing waveform”) must be mapped to a characterization waveform. Typically, this mapping is performed by measuring the fifty-percent crossing time and the slew of the timing waveform and then selecting the characterization waveform that matches the measured values (as represented by a saturated ramp that is commonly referred to as the “standard ramp”). The delay and output slew of the gate are then obtained from either function evaluation or table interpolation.
A shortcoming of this conventional approach is that since the timing properties of the gate are treated as dependent on input slew and load capacitance only, all timing waveforms with the same slew will result in the same gate delay and output slew values. In other words, although the actual delays may vary significantly, this approach would assign the same delay value to all of these timing waveforms. This approximation is typically inaccurate and can result in flawed timing analysis.